Comments on: AMD Widens Server CPU Line To Take Bites Out Of Intel, Arm https://www.nextplatform.com/2023/06/14/amd-widens-server-cpu-line-to-take-bites-out-of-intel-arm/ In-depth coverage of high-end computing at large enterprises, supercomputing centers, hyperscale data centers, and public clouds. Wed, 12 Jul 2023 00:55:57 +0000 hourly 1 https://wordpress.org/?v=6.7.1 By: Timothy Prickett Morgan https://www.nextplatform.com/2023/06/14/amd-widens-server-cpu-line-to-take-bites-out-of-intel-arm/#comment-211019 Wed, 12 Jul 2023 00:55:57 +0000 https://www.nextplatform.com/?p=142538#comment-211019 In reply to tufttugger.

More or less, yes.

]]> By: tufttugger https://www.nextplatform.com/2023/06/14/amd-widens-server-cpu-line-to-take-bites-out-of-intel-arm/#comment-211017 Tue, 11 Jul 2023 23:48:59 +0000 https://www.nextplatform.com/?p=142538#comment-211017 What would 3D-vcache AND HBM3 on the same CPU package look like?… like the MI300C, 96 Genoa core variant. The 6nm I/O dies that the CPU dies are stacked on will have cache.

]]> By: John https://www.nextplatform.com/2023/06/14/amd-widens-server-cpu-line-to-take-bites-out-of-intel-arm/#comment-210020 Thu, 15 Jun 2023 13:14:37 +0000 https://www.nextplatform.com/?p=142538#comment-210020 Interesting article, I can see the clouds and HPC (my main interest really) going for the new servers.

]]> By: TopoMadness https://www.nextplatform.com/2023/06/14/amd-widens-server-cpu-line-to-take-bites-out-of-intel-arm/#comment-210003 Thu, 15 Jun 2023 07:25:24 +0000 https://www.nextplatform.com/?p=142538#comment-210003 Is the Zen-4c 16 Core CCD a unified 16 core design where all 16 cores have access to the CCD’s Full Complement of L3 cache or is that just 2, 8 core CCX units on one CCD there with a topology that’s similar to Zen-2’s and each CCX-Unit(Even ones on the same CCD) having to communicated with each other via the I/O Die in a roundabout way? And that would require the least amount of re-engineering but still have 8 cores sharing the same L3 with the other 8 core CCX on the same CCD looking logically like a separate CCD as far as the logical topology was concerned. And I have read some semianalysis content about Zen-5c being a new Unified 16 Core design with what was called “ladder” L3 cache and some new unified 16 core CCD topology there. AMD needs to Include a CCD and I/O die Topology Diagram with for Each Zen generation to avoid confusion there with regards to the CCX/CCD core groupings and how they communicate via the I/O die on Zen-2/later Zen generations. The Zen-1 Zeppelin Die was the only Zen generation where the Compute-Complex-DIEs actually directly communicate with each other as there was no I/O die on that Zen-1/MCM Topology.

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