https://www.nextplatform.com/2021/09/07/the-cxl-roadmap-opens-up-the-memory-hierarchy/ In-depth coverage of high-end computing at large enterprises, supercomputing centers, hyperscale data centers, and public clouds. Mon, 13 Sep 2021 20:22:28 +0000 hourly 1 https://wordpress.org/?v=6.7.1 https://www.nextplatform.com/2021/09/07/the-cxl-roadmap-opens-up-the-memory-hierarchy/#comment-165924 Fri, 10 Sep 2021 20:39:26 +0000 https://www.nextplatform.com/?p=139172#comment-165924 Shifting persistent memory (PM) to the far side of a CXL connector looks like a great idea, since PM tends to lag DRAM a bit in performance. You thus free up the CPUs’ scarce DDR slots for higher-performing DRAM, while allowing lots of PM in the same system.

]]> https://www.nextplatform.com/2021/09/07/the-cxl-roadmap-opens-up-the-memory-hierarchy/#comment-165877 Wed, 08 Sep 2021 04:50:56 +0000 https://www.nextplatform.com/?p=139172#comment-165877 Interestingly, could CXL be a very good CPU-CPU board level interconnect too .. but it’s not mentioned in the Intel talk?

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