Memory performance is gated primarily by memory device design, organization and access not the interconnect used to access it. Increasing interconnect speed provides modest incremental improvement which is why processor vendors have focused on increasing the number of DDR memory channels at great cost and increased system complexity. This increased cost and complexity were the primary reason behind using serial interconnects to augment and perhaps one day replace DDR. Unlike DDR, serial interconnects rely on a media controller to abstract memory–underlying device type, number, access, etc. In essence, a media controller splits off the lower half of a memory controller which allows memory devices, functionality (caching, accelerator, etc.), mechanical module packaging, etc. to be optimized in ways that processor memory controllers could never support. As such, media controller innovation will ultimately drive system performance which will enable processor simplification as large memory channel pin counts and memory controller complexity are eliminated along with the accompanying power consumption. Ultimately, the interconnect itself won’t matter that much as everything is data access is once again simplified to be basic reads and writes.

We might need local DDR until PCI-Express 6 or 7. But in a funny way, I think flash has to be the new tape, and we need to figure out a way to add a lot more memory to the CPUs. A lot more.