Not sure if they can be converted to a less intensive set of vectors and run through the clone AVX-512. Eventually they will have Xilinx DSP engines doing the math.

… or might they bake themselves some EPYC CPO NoC and do away with external switches?

A hardware system (pool of heterogeneous units) that reconfigures itself (connection-wise) dynamically to match an executing program’s computational graph (code) and data access patterns?

Maybe we literally need lego blocks of compute all linked by fast interconnects and we literally build a system for a particular workflow by connecting stuff. No more static configurations at all. I mean, imagine how much fun would it be to breadboard such a machine? Literally snapping things together and then pouring data in one end and getting answers at the other end. When the task is done, reconfigure and do a different workflow.

Maybe making FPGAs better and cheaper and faster and making electricity way, way cheaper is the real answer. I keep coming to this conclusion. That general purpose compute is actually an illusion unless it is completely reconfigurable.

I see your points (you could both be right), but I remember a time when the FPU was a separate chip (eg. 8087, 80287), the MMU was also a separate IC (AMD fixed that before Intel), and, these days, separate northbridges are also disappearing in favor of in-package I/O dies. Contemporary FPUs and MMUs in particular are programmable through the CPU’s ISA, as are current vector units, and one may hope (maybe) that future GPUs get similarly tightly integrated with CPUs, and into a unified instruction-space (no more need to separately feed the external data-hungry beast).

Then again, if the data processing pipeline through the GPU is too distinct from that of the CPU (eg. uncommonly systolic) these offsprings may need to be kept separated (each calling the other to “come out and play” on an as needed basis).

Are there interesting plans for acceleration subsystems of this type at AMD R’n’D, maybe involving FPGAs, that VP Lynn Comp could relate to the TNP audience (if they are not overly secret)? I would imagine that HPC-specific subsystems (for example) might be restricted to related SKUs, and possibly optionally activated? Is this an important area of activity targeted by the AMD server group?

Maybe these (above) could be questions for a follow-up interview …

Myth 6: Datacenters and factories are best located in Austin, TX, as compared to Asheville, NC.

Question: How do you view (at present and in the future) cloud-based vs on-premise HPC (eg. in light of DOE and SC23)?

Mythwise (to this TNP reader) there isn’t much controversy in the 5 that were discussed. For example, we’ve seen how Frontier moved the Pareto curve for both performance and efficiency (simultaneously), and expect no less from MI300A and its siblings. SMT has its advantages in the datacenter and could be pushed to 4 or 8 threads on some SKUs, as suggested by the interviewer. The competition from ARM is interesting, and it seems to me that AMD could easily CSS-copy-paste itself some Neoverses unto MI300N and MI300V APUs for those customers that want this option, or even just for fun!